Low profile stacked semiconductor chip package

Details Low profile stacked semiconductor chip package Low profile stacked semiconductor chip package

2005-12-14

2008-08-12

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257S778000, C257S774000, C257SE23011

Reexamination Certificate

active

07411285

ABSTRACT:
A stacked semiconductor chip package comprising a first semiconductor chip having an upper surface, a lower surface opposed to said upper surface, and a plurality of conductive metal lines formed on said upper surface of said first semiconductor chip; a plurality of metal elements each having a first arm portion located on said upper surface of said first semiconductor chip and connected electrically to a corresponding one of said metal lines, a second arm portion located on said lower surface of said first semiconductor chip; and a second semiconductor chip having a lower surface and a plurality of conductive bumps provided on said lower surface, and mounted on said upper surface of said first semiconductor chip in such a manner that said solder bumps of said second semiconductor chip is electrically connected to said corresponding conductive metal lines on said upper surface of said first semiconductor chip.

REFERENCES:
patent: 6577013 (2003-06-01), Glenn et al.
patent: 6774473 (2004-08-01), Shen
patent: 6856026 (2005-02-01), Yamada et al.
patent: 7276799 (2007-10-01), Lee et al.
patent: 2004/0119162 (2004-06-01), Egawa
patent: 2004/0207049 (2004-10-01), Bauer et al.
patent: 2005/0014311 (2005-01-01), Hayasaka et al.

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