Low profile semiconductor package

Details Low profile semiconductor package Low profile semiconductor package

2002-12-16

2003-12-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S127000

Reexamination Certificate

active

06669738

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of semiconductor assembly, and more particularly to a low profile semiconductor device and a method for forming the device.
BACKGROUND OF THE INVENTION
Miniaturization of electronic components such as consumer electronics and industrial equipment is a typical objective of design engineers and results in a more desirable and, typically, a lower cost product. To aid with the miniaturization of electronic components, it is a goal of semiconductor device manufacturers to offer packages having progressively thinner profiles and a smaller outlines.
One type of conventional semiconductor assembly, a thin small outline package (TSOP), comprises the use of a thinner lead frame and silicon die, bond wires having a decreased loop, and a thinner encapsulation layer surrounding the die in an attempt to form a smaller, thinner package. Another type of conventional semiconductor device assembly, depicted in
FIGS. 1A and 1B
, is referred to as a ball grid array or “BGA” device. BGA devices typically comprise a resin substrate
10
having one or more layers of traces therein (not depicted) which in effect provides a small printed circuit board (PCB). The device further comprises an array of pads on the bottom of the substrate to which solder balls
12
are attached. A noncircuit surface of a semiconductor die
14
is mounted to a side of the substrate opposite the balls
12
. Bond pads
16
on the die
14
are wire bonded
18
to the traces
20
of the substrate
10
, and then the die
14
, the bond wires
18
and at least a portion of the traces
20
and the substrate
10
are encased in encapsulation material
22
such as plastic. The solder balls
12
on the BGA are contacted with pads on a PCB or socket (not depicted), then the solder
12
is reflowed to electrically couple the BGA with the PCB or socket. Ceramic equivalents to this design are also known in the art as are similar devices having leads instead of balls.
While decreasing the size and cost of components such as microprocessors, memory, and logic devices are goals of designers, the design described above has elements that are contrary to optimal component size. For example, to provide trace portions to allow wire bonding, the substrate must be larger than the die. The bond wires thereby extend laterally from the die to the traces on the substrate, and the device design results in the packaged BGA requiring additional lateral space beyond that required by the die alone. With regard to economy, the multi-layered substrates required by most BGA applications can be relatively expensive.
Further, the additional heat generated as device speeds increase contributes to component failure, and a package design which efficiently dissipates heat is an engineering design goal. A less costly BGA device having a smaller footprint and improved heat dissipation than previous devices would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device having a design that can result in a smaller semiconductor package. In accordance with one embodiment of the invention a semiconductor device comprises an unpackaged semiconductor wafer section having a major surface with a plurality of bond pads thereon. The embodiment further comprises a plurality of conductors each having at least a portion covered by a matrix and a plurality of lead members. The conductor/matrix assembly is attached to the major surface of the wafer section. An electrical connection electrically couples at least one bond pad with a respective lead member, and a sealing material contacts at least the bond pads and the lead members. Other embodiments are also described.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.


REFERENCES:
patent: 3663868 (1972-05-01), Noguchi et al.
patent: 4622574 (1986-11-01), Garcia
patent: 4901136 (1990-02-01), Neugebauer et al.
patent: 4922324 (1990-05-01), Sudo
patent: 5045921 (1991-09-01), Lin et al.
patent: 5218234 (1993-06-01), Thompson et al.
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5302849 (1994-04-01), Cavasin
patent: 5360992 (1994-11-01), Lowrey et al.
patent: 5583378 (1996-12-01), Marr et al.
patent: 5753974 (1998-05-01), Masukawa
“Z-Axis Conductive Adhesive”, Zymet Inc., 7 Great Meadow Lane, E. Hanover, NJ 07936, Aug. 1, 1990.

Affiliated with

Also associated with

Rating

Low profile semiconductor package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low profile semiconductor package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low profile semiconductor package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3120458