Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Patent
1995-06-07
1998-10-20
Ledynh, Bot L.
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
257678, H01L 2302
Patent
active
058249508
ABSTRACT:
A semiconductor die carrier configured to be secured to a printed circuit board includes an insulative package for housing a semiconductor die. The insulative package has a top surface, a bottom surface, and a plurality of side surfaces coupling the top surface and the bottom surface. At least one row of electrically conductive leads extends from at least one of the side surfaces of the insulative package. Each of the leads has a proximal end, at least one horizontal portion extending in a horizontal direction, at least one vertical portion extending in a vertical direction, and a distal end. The distal ends of the leads are configured to be secured to the printed circuit board such that, when the distal ends of the leads are secured to the printed circuit board, at least a portion of the insulative package is located below an upper surface of the printed circuit board.
REFERENCES:
patent: 3337838 (1967-08-01), Damiano et al.
patent: 3366915 (1968-01-01), Miller
patent: 3444506 (1969-05-01), Wedekind
patent: 3676748 (1972-07-01), Kobayashi et al.
patent: 3676993 (1972-07-01), Bergey et al.
patent: 3806831 (1974-04-01), Kleinberg
patent: 4167647 (1979-09-01), Salera
patent: 4331831 (1982-05-01), Ingram et al.
patent: 4423468 (1983-12-01), Gatto et al.
patent: 4437718 (1984-03-01), Selinko
patent: 4487463 (1984-12-01), Tillotson
patent: 4572604 (1986-02-01), Ammon et al.
patent: 4616406 (1986-10-01), Brown
patent: 4655526 (1987-04-01), Shaffer
patent: 4660069 (1987-04-01), Kochanski et al.
patent: 4675472 (1987-06-01), Krumme et al.
patent: 4698663 (1987-10-01), Sugimoto et al.
patent: 4705917 (1987-11-01), Gates, Jr. et al.
patent: 4734042 (1988-03-01), Martens et al.
patent: 4766479 (1988-08-01), Krum et al.
patent: 4897055 (1990-01-01), Jurista et al.
patent: 4931908 (1990-06-01), Boucard et al.
patent: 4943846 (1990-07-01), Shirling
patent: 4975066 (1990-12-01), Sucheski et al.
patent: 4989318 (1991-02-01), Utunomiya et al.
patent: 4997376 (1991-03-01), Buck et al.
patent: 5008734 (1991-04-01), Dutta et al.
patent: 5022144 (1991-06-01), Hingorary
patent: 5037311 (1991-08-01), Frankeny et al.
patent: 5049974 (1991-09-01), Nelson et al.
patent: 5071363 (1991-12-01), Reylek et al.
patent: 5081563 (1992-01-01), Feng et al.
patent: 5091772 (1992-02-01), Kohara et al.
patent: 5123164 (1992-06-01), Shaheen et al.
patent: 5137456 (1992-08-01), Desai et al.
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5182853 (1993-02-01), Kobayashi et al.
patent: 5220491 (1993-06-01), Sugano et al
patent: 5281151 (1994-01-01), Arima et al.
patent: 5283717 (1994-02-01), Hundt
patent: 5285104 (1994-02-01), Kondo et al.
patent: 5309024 (1994-05-01), Hirano
patent: 5326936 (1994-07-01), Taniuchi et al.
patent: 5327325 (1994-07-01), Nicewarner, Jr.
patent: 5334279 (1994-08-01), Gregoire
patent: 5342999 (1994-08-01), Frei et al.
patent: 5347429 (1994-09-01), Kohno et al.
patent: 5351393 (1994-10-01), Gregoire
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5390412 (1995-02-01), Gregoire
patent: 5403784 (1995-04-01), Hashemi et al.
patent: 5428505 (1995-06-01), Sakemi et al.
patent: 5438224 (1995-08-01), Papageorge et al.
patent: 5541449 (1996-07-01), Crane, Jr. et al.
patent: 5543586 (1996-08-01), Crane, Jr. et al.
patent: 5659953 (1997-08-01), Crane, Jr. et al.
patent: 5696027 (1997-12-01), Crane, Jr. et al.
Dimensional Circuits Corporation, Dimensional Circuits Corp. Awarded Two U.S. Patents, D.C.C. News, Apr. 5, 1994.
Robert Barnhouse, "Bifurcated Through-Hole Technology--An Innovative Solution to Circuit Density," Connection Technology, pp. 33-35 (Feb., 1992).
"AMP-ASC Interconnection Systems," AMP Product Information Bulletin, pp. 1-4 (1991).
"Micro-Strip Interconnection System," AMP Product Guide, pp. 3413-3414 (Jun., 1991).
"Rib-Cage II Through-Mount Shrouded Headers and Micropax Board-to-Board Interconnect System," Du Pont Connector Systems Product Catalog A, pp. 2-6, 3-0, 3-1, (Feb., 1992).
R.R. Tummala et al., "Microelectronics Packaging Handbook," Van Nostrand Reinhold, 1989, pp. 38-43, 398-403, 779-791, 853-859, and 900-905.
"Packing," Intel Corporation, 1993, pp. 2-36, 2-96, 2-97, 2-100, 3-2, 3-24, and 3-25.
J.W. Balde et al., "New Chip Carrier Package Concepts," Computer, Productivity and Automation, IEEE Computer Society, vol. 10, pp. 58-68, (Dec., 1977).
Mosley Joseph M.
Portuondo Maria M.
Taylor Drew L.
Ledynh Bot L.
Soderquist Kristina
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