Low profile, high density memory system

Details Low profile, high density memory system Low profile, high density memory system

2001-04-13

2002-04-30

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C361S790000, C361S769000

Reexamination Certificate

active

06381164

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to high density, low profile electronic packages and, more particularly, to the high density, low profile packaging of high performance, high density memory modules having impedance-controlled transmission line buses and, optionally, driver line terminators built into the modules, for maintaining high electrical performance.
BACKGROUND OF THE INVENTION
The current trend in electronic package design for use in high speed electronic systems is to provide high electrical performance, high density and highly reliable interconnections between various circuit devices, which form important parts of those systems. The system may be a computer, a telecommunications network device, a handheld “personal digital assistant”, medical equipment, or any other electronic equipment.
High reliability for such connections is essential due to potential end product failure, should vital misconnections of these devices occur. It is also very important that the interconnections be as dense as possible, use the least possible amount of real estate on the printed circuit board, and provide minimal impact on the printed circuit board wiring. In some cases, such as for laptop computers and handheld devices, it is very important that the height of the connectors and the auxiliary circuit members be as low as possible.
As system density and performance have increased so dramatically, so have the stringent specifications for interconnections. One way high electrical performance is manifested is in improved signal integrity. This can be accomplished by providing the interconnections with shielding that helps them to more closely match a desired system impedance. These demanding requirements, especially when coupled with the requirement for field-separability, have led to a wide variety of possible connector solutions.
Also, to assure effective repair, upgrade, and/or replacement of various components of the system (e.g., connectors, cards, chips, boards, modules, etc.), it is desirable that the connections be reworkable at the factory. It is also highly desirable in some cases that, within the final product, such connections be separable and reconnectable in the field. Such a capability is also desirable during manufacture in order to facilitate testing, for example.
A land grid array (LGA) is an example of such a connection in which each of two primarily parallel circuit elements to be connected has a plurality of contact points, arranged in a linear or two-dimensional array. An array of interconnection elements, known as an interposer, is placed between the two arrays to be connected, and provides the electrical connection between the contact points or pads. For even higher density interconnections, additional parallel circuit elements may be stacked and electrically connected through additional LGA connectors to create three-dimensional packages. In any case, since a retentive force is not inherent as in a pin-and-socket type interconnection, a clamping mechanism is needed to create the force necessary to ensure each contact member is compressed an appropriate amount during engagement to form the required interconnections to the circuit elements. While LGA interposers are implemented in many different ways, the implementations of most interest are those described in the aforementioned copending U.S. patent applications.
For applications such as high-speed memory buses for use in modern, high-speed digital computers, the sophisticated software running on them requires large amounts of volatile random access memory (RAM) at ever-increasing bus and clock speeds. To ensure fast memory cycle times, extremely short, fast rise pulses are used. The electrical drive requirements for servicing the large number of memory devices has become much more stringent than when slower memory was in use.
The maximum operating speed of a memory system is largely determined by the electrical interconnections between the memory controller and the memory devices, or the bus. As data rate increases, signal propagation times through the interconnections are no longer negligible compared to the transition time of the signals. At high bus speeds, these interconnections behave as transmission line networks. The response characteristics of such transmission line networks, therefore, determine the maximum usable speed of the memory bus.
In the current generation of low profile memory packaging technology, the amount of memory physically available on a system is determined by the capacity of the memory devices (chips) themselves and the number of physical electrical connections on individual cards or modules, and the amount of space available to support additional memory cards. The capacity of the line drivers or receivers is another limiter to the number of cards or modules which may be daisy chained.
In conventional random access memory systems, because only one bit can exist on the bus during a certain time interval, the bus speed is determined mainly by the signal setup time of the bus. As a result, the highest achievable data rate for such buses in PC memory systems at present is 266 Mbits per second. Usually, no impedance-matching termination is required or provided in such a conventional RAM system.
At first viewing some of the elements of U.S. Pat. No. 5,963,464, issued to Dell et al. for STACKABLE MEMORY CARD, appear similar to those of various embodiments of the present invention. However, further study shows significant differences. The embodiment depicted in FIGS. 1-3 of DELL is a stackable memory card design. The embodiment depicts a stackable memory. card with connector sockets attached to the top surface and connector pins attached to the bottom surface of each card. Mating sockets are included on the motherboard. While this packaging technology might work adequately with slower memory bus technology, the unshielded inductive connector pins represent enough of an electrical discontinuity to generate significant reflections and electrical noise. Furthermore, the unused sockets on the top surface of the topmost card act as antennae for stray RF pickup. From a reliability/manufacturing point of view, the pin-and-socket approach leaves open the possibility of module damage even if only one pin or socket is bent or otherwise damaged. In such cases, the card must be either reworked or scrapped.
While a RAMBUS®-based memory module has been chosen for purposes of disclosure, it should be obvious that the principles taught by the instant invention can be applied not only to other high speed memory modules, such as Double Data Rate (DDR) SDRAM, but also to a wide variety of electronic packaging structures for many other applications requiring high speed and high performance including but not limited to microprocessor-based, digital signal processor-based, and telecommunications-based applications and subsystems.
To achieve even higher bus speeds and, at the same time, allow for larger memory capacities, impedance controlled types of buses must be adopted. For example, RAMBUS technology, created by Rambus Inc. of Mountain View, Calif. features a memory configuration wherein memory devices are disposed (packaged) on up to three RAMBUS Inline Memory Module (RIMM) cards all interconnected on a motherboard by a high-speed data bus. One or more termination components are placed on the motherboard at the physical end of the bus.
In operation, address/data lines leave driver circuits on the motherboard and enter a first RIMM card in the memory chain. These same address/data lines must leave the RIMM via a complete, second set of connections. This routing continues through a second and sometimes a third RIMM module before the driver lines reach their terminations. This memory/bus configuration allows very fast transit signals to be transmitted between a memory controller and a data storing device over relatively long buses. These buses allow multiple bits to propagate simultaneously down each line of the bus, thereby achieving access data rates of 800 Mbits per second. Even higher bus rat

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