Low profile exposed die chip carrier package

Details Low profile exposed die chip carrier package Low profile exposed die chip carrier package

1995-10-11

1997-12-09

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361761, 257684, H05K 118

Patent

active

056966660

ABSTRACT:
An integrated circuit package (10) comprises a semiconductor die (12), and a substrate (14) having a through-cavity opening (22) for receiving the semiconductor die. The bottom side of the substrate has solder pads (24) arranged as a peripheral pad grid array. The semiconductor die is wire bonded (26) to the to the top side of the substrate. An encapsulant (16) seals the top surface of the semiconductor die and circuitry, and portions of the top side of the substrate. The bottom surface of the semiconductor die remains exposed to the atmosphere, eliminating moisture-related die attach delamination issues and improving heat transfer away from the semiconductor die. Furthermore, the reduced contribution of the semiconductor die to overall package height results in an ultra low profile package.

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Conference Publication 44th Electronic Components & Technology Conference, May 1 - May 4, 1994, Washington, D.C. 1994 Proceedings, pp. 67-74, IEEE.

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