Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-08-14
2002-09-17
Chaudhuri, Olik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S131000
Reexamination Certificate
active
06452248
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to one-time programmable elements in an integrated circuit.
Fuses are frequently used in IC designs for a low-density, non-volatile circuit configuration. A fuse is typically made of a narrow line of metal or poly layer or of a conductive layer material available in an IC process, which can be melted when sufficient Joules heating occurs with sufficient current passing through the fuse. Power dissipated as heat is proportional to the fuse resistance and the square of the current, P=R*I*I.
Typical requirements and constraints of design and programming of fuses are:
High current (0.3 amps and higher) is needed to raise enough temperature to melt fuses.
If the parasitic path resistance is high, a power source capable of outputting a high voltage at high current is needed.
Two probe pads or pins physically near each other are needed to minimize parasitic internal resistance and to allow passing high current. A common pad or pin can be shared, but at least one probe pad or pin per fuse is required.
Melted metal or poly has to be physically displaced, requiring exposure to empty space (air) typically realizable with a passivation opening. Exposed fuses can be subject to contamination, corrosion, and material regrowth.
The advantage of conventional fuse use is that it is a simple, inexpensive, brute-force way to realize a one-time programmable element. The disadvantages of conventional fuse and its use are many, and among them are:
High current programming requiring elaborate optimized timing and circuitry.
IC chip is subject to transients and spikes with high-current steering.
Probe pads or pins wasting valuable silicon space especially for pad-limited designs.
High-temp (>450C) stressful event; material is melted and spread.
Questionable reliability of blown and unblown fuses.
Programming must be done before final packaging, therefore doubling the test costs.
Fuse trimming not done on final performances of final parts→potential yield fallout.
Fuses cannot be selected with internal logic. Their programming is determined by which probe pads or pins current are applied.
In addition to fuses, semiconductor ROMs and PROMs provide one-time programmable memories. A ROM is typically made at the time the wafer is made, with the programming being done with the interconnect layer of aluminum. PROMs are electrically programmable after final packaging. Early PROMs used a nichrome fuse. Nichrome, an alloy of nickel and chrome, was deposited as a very thin film link to column lines of the PROM. Heavy currents caused this film to blow, opening up the connection between the PROM column lines.
A later type of PROM uses a polycrystalline silicon as a fuse. The fuse is blown with a pulse train of increasingly wider pulses with a current of 20-30 mA typically needed to blow the fuse. During this operation, temperatures estimated at 1400° C. are reached in the notch of the polysilicon fuse. At these temperatures, the silicon oxidizes and forms an insulating material.
Yet another type of PROM uses a bipolar junction. A diode is reverse-biased, and the heavy flow of electrons in a reverse direction causes aluminum atoms from the emitter contact to migrate through the emitter to the base, causing an emitter-to-base short.
In MOS technology, erasable PROMs are formed using a floating gate which can have charge placed on it and then removed either with ultraviolet light or electrically.
SUMMARY OF THE INVENTION
The present invention provides a programmable fuse structure using an MOS transistor. A voltage potential is switched across the gate of the MOS transistor, with the gate resistance causing it to heat the MOS structure. This causes a short at one or more of a number of locations in the MOS structure, thereby programming the MOS transistor.
In one embodiment, one side of the gate is connected to ground, and the ate is actually a number of gates connected in parallel to provide increased heating. The ate is made of polysilicon which is a more efficient heating structure than metal used in metal fuse. The gate has a thickness of less than 0.5 microns.
A programming circuit with the MOS transistor in a feedback path is provided. This feedback provides a self-timing feature, such that immediately after the fuse is programmed, its programming operation ceases. This prevents unnecessary heating and wasting of power. An additional function of the programming circuit is to ensure that the fuse is not accidentally or unintentionally programmed.
In order to improve the efficiency of programming, the switching device is impedance matched with polysilicon fuse gate of the MOS structure. In addition, the MOS layout is optimized for MOS thermal-related failures.
The purpose of this invention is to create a reliable, low-current, low-temperature, low-powered, pad-less, completely passivated, high-density, logic-selectable, one-time programmable element and its support circuitry. The device can be selected and programmed at final test using logic, and uses the internal chip power supply. It can also be one-time programmed during normal operation at any time to a recalibrate performances or adjust chip parameters. It does not need to be exposed and probe pads or pins are not required, hence it can be placed anywhere in a chip as many times as it is needed.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4757359 (1988-07-01), Chiao et al.
patent: 5212102 (1993-05-01), Iranmanesh et al.
patent: 5291434 (1994-03-01), Kowalski
patent: 5311039 (1994-05-01), Kimura et al.
patent: 5888873 (1999-03-01), Krivokapic
“memory design handbook”, Intel Corporation 1977.
Chaudhuri Olik
Exar Corporation
Townsend and Townsend / and Crew LLP
Vesperman William
LandOfFree
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