Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-10-24
2003-09-09
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C323S315000, C330S288000
Reexamination Certificate
active
06617915
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to analog circuits, and more particularly to low power current mirrors.
2. Description of the Related Art
Current mirrors are important building blocks of any analog design. Some of the desired qualities of a current mirror include accuracy in mirroring the current from input to output, which can require a high level of transistor matching, a high output impedance to reduce mirroring errors at varying output voltage levels, and high bandwidth, especially when the current mirror is in the signal path. Other desirable attributes of a current mirror may include low voltage operation, low power consumption, and low operating head room for input and output terminals, which is the lowest voltage to be maintained at the input and output of the mirror for proper functioning.
Unfortunately, the majority of current mirrors cannot be designed to achieve all of the above listed qualities and are typically designed specifically for their application environment. Maximizing a single quality will most likely result in the compromise of another.
A basic current mirror is formed by two MOS transistors. The first transistor is coupled as a diode-connected device and generates a bias voltage in response to an input current. The second transistor receives the bias voltage at a gate terminal and generates an output current at its drain terminal which is proportional to the input current. A common adaptation to the basic current mirror is a cascode current mirror, implementing an additional pair of transistors, one each in series with the transistors of the basic current mirror configuration.
FIGS. 1-3
are schematic illustrations of various current mirrors of the prior art. Basic current mirror structure is illustrated in
FIG. 1. A
conventional current mirror
100
is consists of a current source biasing circuit formed from a diode-connected transistor
102
and an output current source formed with a single output transistor M
2
104
. In
FIG. 1
, transistor
102
receives an input current I
in
and generates a bias voltage in response which is received by the transistor M
2
104
at its gate terminal. Transistor M
2
104
generates an output current I
out
at its drain terminal. Although the current mirror
100
of
FIG. 1
implements a simple design, there are significant drawbacks. There is very little signal room at the input, which is limited by the matching of the design, and low output impedance. A low output impedance can generate mirroring errors due to changes in drain-to-source voltage drops of the output transistor M
2
104
. Low output impedance can also account for reduced gains when the mirror is used as an active load. The gain can be enhanced by adding cascode transistors, which reduces the drain modulation of the transistors and boosts the impedance.
An exemplary cascode current mirror
200
of the prior art is illustrated in
FIG. 2
where a transistor
152
receives an input current and a transistor
154
, having a common gate bias voltage, V
bias
, with transistor
152
, generates an output current. Transistors
152
and
154
have been added to boost the impedance of the input and output nodes of the mirror illustrated in FIG.
1
. Transistor
202
and transistor
152
are coupled in series, and transistors
154
and
204
are coupled in series. Transistors
202
and
204
have a common gate connection which is coupled to the drain of transistor
152
. Transistor
202
generates the bias voltage for transistor
204
. With the added stage, the mirror input still requires a gate-to-source transistor voltage drop, and the input signal room is reduced.
The enhanced impedance current mirror of
FIG. 2
can be improved at the cost of power with the wide-swing current mirror
300
illustrated in FIG.
3
. Instead of applying the input current I
in
to the drain of transistor
152
, it is injected at the drain of transistor
202
, and only a bias current I
bias
302
is applied to transistor
152
.
The wide-swing current mirror
300
has a very high input signal room such that it only requires a drain-to-source voltage drop (usually less than 150 mV) to operate. Transistors
152
and
202
form a closed current-to-voltage amplifier loop such that, at zero input current, only the bias current is mirrored to the output. In operation, injection of current at the input node lowers the gate-to-source voltage of transistor
152
, which in turn increases the gated drive of transistor
202
. Transistor
202
drains the extra current injected to the input node, which is mirrored to transistor
204
. Drawbacks to this design include the need for a bias current to be continuously operating, and the high power consumption due to the high bias current being mirrored to the output in addition to the input current. In addition, for high bandwidth applications the pole of the mirror needs to be carefully placed beyond the signal bandwidth, which requires a sufficient bias current. This increased bias current causes the mirror to consume excessive power, especially at mirroring ratios greater than one.
Analog designs aimed to operate from a voltage source in the range of 1 Volt generally cannot afford to have two gate-to-source transistor voltage drops on one voltage supply to ground path (cascode current mirror). Such voltage drops may not be a problem when the mirror is used simply as a current source, wherein the input head room is one gate-to-source transistor voltage drop and is of low importance. However, if a current signal from a differential pair or an intermediate stage of a circuit is the subject of the current mirror, the input operating voltage, which is typically at least one gate-to-source transistor voltage drop, makes the two gate-to-source transistor voltage drops intolerable for operation.
Many improvements have been made to the basic current mirror, however, many adaptations result in disadvantages such as low output resistance, reduced signal room, and high power consumption. Therefore, a current mirror overcoming such disadvantages is needed in the art.
SUMMARY OF THE INVENTION
A current mirror circuit, comprising a bias current input port, a signal current input port, an output current port, a mirroring circuit receiving said bias current and said signal, and a bias current sink connected to said mirroring circuit so as to shunt said bias current to circuit common. The bias current sink may comprise a transistor receiving a gate bias voltage, the signal current, and be connected in parallel with the mirroring circuit. The mirroring circuit can be a cascode mirroring circuit.
A wide swing current mirror circuit has an input stage and an output stage, wherein a bias current is separated from a signal current at the input stage, and wherein a bias current sink is connected in parallel with at least a portion of the input stage such that the bias current is not mirrored to the output stage. The bias current sink can be a transistor having a gate bias voltage.
A method of reducing power consumption in a current mirror, comprising routing a bias current and a signal current to circuit common via different paths, such that the bias current is not mirrored to an output of the analog current mirror. Routing the bias current to circuit common may include a bias current sink transistor having a gate bias voltage.
A circuit for mirroring an electrical current, comprising a bias current input terminal, a signal current input terminal, and five transistors. The first transistor has a biased gate terminal and a drain terminal which receives the bias current, and the second transistor has a gate terminal connected to the gate terminal of said first transistor. The third transistor has a drain terminal connected to the source terminal of the first transistor, a gate terminal connected to the drain terminal of the first transistor, and a source terminal connected to ground. The fourth transistor has a drain terminal connected to the source terminal of the second transistor, a gate terminal connected to the gate terminal
Knobbe Martens Olson & Bear LLP
Lam Tuan T.
Zarlink Semiconductor (U.S.) Inc.
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