Low power wide bandwidth programmable gain CDS...

Amplifiers – With periodic switching input-output

Reexamination Certificate

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C330S292000

Reexamination Certificate

active

06573784

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits. More particularly, embodiments of the invention relate to a method and circuitry for implementing a low-power wide-bandwidth programmable-gain amplifier.
For charge-coupled-device (CCD) based digital cameras having greater than 1 million pixels, an analog front end (AFE) is needed for processing the CCD signals.
High-gain and high-speed are important requirements for CCD digital cameras, as well as for other handheld and portable consumer devices. Correlated double sampling amplifiers (CDS-amp) are employed within AFEs at the front end. CDS-amps should have a programmable gain of 6 or 12 dB with fast settling requirements due to full signal swings from pixel to pixel at 30 MSPS. Because the prior art employs operational amplifiers (op-amps) to provide high-gain, parasitics from the op-amp elements (resulting in lower bandwidth) cause a slowing effect.
Low-noise is another important requirement for CCD digital cameras. To improve the overall system signal-to-noise ratio (SNR) of an AFE, or any instrumentation amplifier system, as much signal gain as the technology allows should be applied in the first input stage of the AFE. A problem is that the state of the art technology should sufficiently amplify the signal yet minimize noise at the first input stage of the AFE. In a CCD digital camera, a CDS-amp in the AFE might provide sufficient gain. However, because the prior art uses full op-amps to provide this gain, more inherent noise is present in such systems.
Low power is another important requirement. Handheld and portable consumer devices can be smaller and lighter when they consume lower power because battery sizes can be small and lighter. The power dissipation of the prior art can be in excess of 25 mW.
U.S. Pat. No. 4,287,441 describes a CDS-amp which is power hungry and has a lower bandwidth (about 20 MHz) because it requires the use of full op-amps to implement the CDS-amp.
A paper, “Instrumentation Amplifiers: Versatile Differential Input Gain Blocks” describes an instrumentation amplifier which used full op-amps. Application Note AN-75, Burr Brown Handbook of Linear IC Applications, Burr Brown, Tucson, Ariz., 1987.
Instrumentation amplifiers made by Analog Devices, part AD522, and Burr Brown (now Texas Instruments), INA101, so-called Triple Op-amp Instrumentation Amplifiers IC chips, use three op-amps.
Thus, there is a need for an improved amplifier circuit that can be used in correlated double sampling. The circuit should be a high-gain high-speed circuit. This circuit should also be a low-noise low-power circuit.
BRIEF SUMMARY OF THE INVENTION
The present invention achieves the above needs with a method and circuitry for implementing amplifiers. More particularly, embodiments of the present invention provide methods and circuitry to achieve a low-power wide-bandwidth programmable-gain amplifier that used as a CDS-amp or an instrumentation amplifier. The circuit also operates at high speeds and low noise.
Embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having as few as one transistor. A current source biases one stage of the two-stage amplifier. A load resistor network couples to the two-stage amplifier and is configured to set the gain value for the two-stage amplifier.
Because the amplifier has as few as two transistors, there are fewer parasitics which enables it to operate at higher speeds, and it dissipates little power and generates little noise, unlike typical op-amps.
In one embodiment, an amplifier circuit includes a first two-stage amplifier and a second two-stage amplifier, each stage having a few as one transistor. A current source biases one stage of each two-stage amplifier. A load resistor network couples between the first and second two-stage amplifiers and is configured to set gain values for the first and second two-stage amplifiers.
In another embodiment the load resistor network is programmable such that the load resistor network can toggle the gain values of the first and second amplifiers between at least two different values.
Embodiments of the present invention achieve their purposes and benefits in the context of known circuit and process technology and known techniques in the electronic and process arts. Further understanding, however, of the nature, objects, features, and advantages of the present invention is realized by reference to the latter portions of the specification, accompanying drawings, and appended claims. Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description, accompanying drawings, and appended claims.


REFERENCES:
patent: 4287441 (1981-09-01), Smith
patent: 5376899 (1994-12-01), Pass
patent: 5703524 (1997-12-01), Chen
patent: 5796361 (1998-08-01), Levinson
patent: 6018269 (2000-01-01), Viswanathan
patent: 6025875 (2000-02-01), Vu et al.
patent: 6118340 (2000-09-01), Koen
Kasha, Dan B. Et Al., “A 16-mW, 120-dB Linear Switched-Capacitor Delta Sigma Modulator with Dynamic Biasing,” IEEE Journal of Solid-State Circuits, vol. 34, No. 7, pp. 921-925, Jul. 1999.
Lewis, Stephen H., “Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, No. 8, pp. 516-523, Aug. 1992.
Mangelsdorf, C., Et Al., “A CMOS Front-End for CCD Cameras,” 1996 IEEE International Solid-State Circuits Conference, pp. 190-191, 1996.
Abo, Andrew M., et al. “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999.
Nakamura, K., et al., “A CMOS Analog Front End Chip-Set for Mega Pixel Camcorders,” 2000 IEEE International Solid-State Circuits Conference, pp. 190-191, 2000.

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