Low power voltage multiplier circuit

Details Low power voltage multiplier circuit Low power voltage multiplier circuit

1980-08-04

1982-08-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307264, 363 60, H02M 3155, H03K 502, H03K 17687

Patent

active

043440037

ABSTRACT:
A voltage multiplier includes an inverter connected at its output to one plate of a capacitor for applying a first or a second voltage thereto, a first transistor switch which, when on, applies a second voltage to the second plate of the capacitor, and a second transistor switch which, when on, couples the second side of the capacitor to a load. For one polarity of input signal the inverter output switches from the first to the second voltage to produce an enhanced voltage at the second plate which is coupled via the second switch to the load. For the opposite polarity of input signal the inverter output switches from the second to the first voltage and the first switch is turned on. The input signal to the inverter is delayed and circuits responsive to the input signals are coupled to the first and second switches for:

REFERENCES:
patent: 3774055 (1973-11-01), Bapat
patent: 3889135 (1975-06-01), Nomiya et al.
patent: 4000412 (1976-12-01), Rosenthal et al.
patent: 4106086 (1978-08-01), Holbrook et al.

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