Low power vector summation method and apparatus

Details Low power vector summation method and apparatus Low power vector summation method and apparatus

2006-08-01

2006-08-01

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S300000

Reexamination Certificate

active

07085794

ABSTRACT:
An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

REFERENCES:
patent: 5696710 (1997-12-01), Hague et al.
patent: 6148319 (2000-11-01), Ozaki
patent: 6874007 (2005-03-01), Denk et al.

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