Low power, TTL level CMOS input buffer with hysteresis

Details Low power, TTL level CMOS input buffer with hysteresis Low power, TTL level CMOS input buffer with hysteresis

1989-12-28

1991-07-23

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307475, 307279, H03K 19094

Patent

active

050346237

ABSTRACT:
A circuit for use as a TTL level CMOS input buffer with hysteresis is disclosed. A first transistor of a first conductivity tupe has its source connected to a first reference voltage. Second and third transistors of opposite conductivity type have their source drain paths connected in series between the drain of the first transistor and a common potential. The gates of the first, second, and third transistors are connected to an input signal. An inverter has its input connected to the drain of the first transistor and has an output. A fourth transistor of the first conductivity type has its gate connected to the output, its drain connected to the series connection between the second and third transistors, and its source connected to a second reference voltage. By appropriately sizing the transistors, the low level trip point and the high level trip point of the circuit may be adjusted. The circuit draws low power during standby. Logic gates may also be designed that incorporate the circuit.

REFERENCES:
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4563594 (1986-01-01), Koyama
patent: 4563595 (1986-01-01), Bose
patent: 4779015 (1988-10-01), Erdelyi
patent: 4786830 (1988-11-01), Foss
patent: 4825106 (1989-04-01), Tipon et al.
patent: 4849653 (1989-07-01), Imai et al.
patent: 4859873 (1989-08-01), O'Shaughnessy et al.

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