Low power TTL/CMOS receiver circuit

Details Low power TTL/CMOS receiver circuit Low power TTL/CMOS receiver circuit

1993-02-10

1994-06-07

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307443, H03K 190185, H03K 190948

Patent

active

053192621

ABSTRACT:
A low power TTL/CMOS receiver circuit consists of four stages, each of which is, respectively, comprised of at least two complementary FET devices connected to each other in series. The various stages control each other by a variety of feedback interconnections. The use of feedback loops permits to significantly decrease the DC current in the input stage of the receiver circuit. It also realizes a substantial decrease in AC current consumption, although less significantly. Finally, delay variations between input and output signals are obtained as well as substantial improvements in the symmetry between the true and complement output signals of the receiver circuit.

REFERENCES:
patent: 4656373 (1987-04-01), Plus
patent: 4672243 (1987-06-01), Kirsch
patent: 4929852 (1990-05-01), Bae
patent: 5021684 (1991-06-01), Ahuja et al.
IBM Technical Disclosure Bulletin, vol. 32, No. 12, May 1990, pp. 411-413, "High Performance CMOS Receiver Circuit For Interfacing With TTL, ECL, NMOS or CMOS Logic Circuits".

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