Low power, three state power up circuit

Details Low power, three state power up circuit Low power, three state power up circuit

1988-09-06

1989-10-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072964, 307592, 307473, H03K 5153, H03K 1716, H03K 1720, H03K 17284

Patent

active

048719269

ABSTRACT:
A circuit for use in conjunction with an enable/disable gate of a three state logic circuit for disabling the outputs of the logic circuit during power up of the voltage supply to maintain a high impedance output state at the outputs of the logic circuits. The circuit includes a voltage level detector stage comprising a switching transistor that is held in a non-conducting state until the voltage supply reaches a predetermined potential after which the transistor is turned on and a pair of transistors configured as a current mirror with their bases coupled to the output of the switching transistor. The pair of transistors are turned on until the switching transistor is turned on to provide sufficient base current drive to a disable transistor of the enable/disable gate such that the logic circuit is disabled accordingly. An aspect of the invention is that the power up circuit draws little additional power during normal operation of the logic circuit.

REFERENCES:
patent: 4339675 (1982-07-01), Ramsey
patent: 4339676 (1982-07-01), Ramsey
patent: 4481430 (1984-11-01), Houk et al.
patent: 4486674 (1984-12-01), Neely
patent: 4488067 (1984-12-01), Kraft et al.
patent: 4745308 (1988-05-01), Neely

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