Low power three-stage CMOS input buffer with controlled switchin

Details Low power three-stage CMOS input buffer with controlled switchin Low power three-stage CMOS input buffer with controlled switchin

1989-06-19

1990-09-18

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307279, 307290, H03K 17687

Patent

active

049580884

ABSTRACT:
A CMOS low power Schmitt type input buffer for a dynamic random access memory (DRAM) circuit. This buffer is further characterized in that a falling edge on the input has better than average noise immunity and has a slightly longer propagation time through the buffer than a rising edge.

REFERENCES:
patent: 4295062 (1981-10-01), Mihalich et al.
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patent: 4461963 (1984-07-01), Koomen
patent: 4506168 (1985-03-01), Uya
patent: 4563594 (1986-01-01), Koyama
patent: 4563595 (1986-01-01), Bose
patent: 4687955 (1987-08-01), Koinuma
patent: 4734592 (1988-03-01), Essig et al.
patent: 4818901 (1989-04-01), Young et al.

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