Low power synchronous memory command address scheme

Details Low power synchronous memory command address scheme Low power synchronous memory command address scheme

2011-05-10

2011-05-10

Phan, Trong (Department: 2827)

Static information storage and retrieval

Hardware for storage elements

C365S189050, C365S194000, C365S230060, C365S230080, C365S233100, C365S233130

Reexamination Certificate

active

07940543

ABSTRACT:
A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.

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