Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Patent
1998-05-05
2000-12-19
Chin, Stephen
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
375262, 375265, 704242, 714795, H03D 1341
Patent
active
061635812
ABSTRACT:
A method, apparatus, and a program storage device useful in performing computations to decode a convolutionally coded sequence without resorting the use of switching elements is disclosed. The method comprises the steps of computing a first branch metric between a first input node and an output node, adding a first input path metric to the first branch metric to produce a first candidate output path metric, computing a second branch metric between a second input node and the output node, adding the second branch metric to a second path metric to derive a second candidate output path metric, and configuring a decision bit based upon the parity of the output state node state and upon whether the first candidate output path metric is greater than the second candidate output path metric. In one embodiment, a comparison between the first and the second candidate output path metrics is compared to the parity of the output node by an exclusive OR gate or a table lookup to determine the decision bit. The invention also is described by an apparatus comprising a means for performing these steps and a program storage device tangibly embodying instructions to perform the steps.
REFERENCES:
patent: 6009127 (1999-12-01), Piirainen
Inyup Kang and Alan N. Willson, Jr., "A Low-Power State-Sequential Viterbi Decoder for CDMA Digital Cellular Applications," IEEE, 1996, pp. 272-275.
Andrew J. Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm," IEEE Transactions on Information Theory, vol. IT-13, No. 2, Apr. 1967, pp. 260-269.
Jim K. Omura, "On the Viterbi Decoding Algorithm," IEEE Transactions on Information Theory, Jan. 1969, pp. 177-179.
G. David Forney, Jr., "The Viterbi Algorithm," Proceedings of the IEEE, vol. 61, N. 3, Mar. 1973, pp. 268-278.
Gerhard Fettweis and Heinrich Meyr, "High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture," IEEE Communications Magazine, May 1991, pp. 46-55.
Peter J. Black and Teresa H. Meng, "A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder," IEEE Journal of Solid-State Circuites, vol. 27, No. 12, Dec. 1992, pp. 1877-1885.
Jerrold A. Heller and Irwin Mark Jacobs, "Viterbi Decoding for Satellite and Space Communication," IEEE Transactions on Communication Technology, vol. COM-19, No. 5, Oct. 1971, pp. 835-848.
Andrew J. Viterbi, "Convolutional Codes and Their Performance in Communication Systems," IEEE Transactions on Communications Technology, vol. COM-19, No. 5, Oct. 1971, pp. 751-772.
Charles M. Rader, "Memory Management in a Viterbi Decoder," IEEE Transactions on Communications, vol. COM-29, No. 9, Sep. 1981, pp. 1399-1401.
B.K. Min and N. Demassieux, "A Versatile Architecture for VLSI Implementation of the Viterbi Algorithm," IEEE, V2.15, 1991, pp. 1110-1104.
C. Bernard Shung, et al., "A 30-MHz Trellis Codec Chip for Partial-Response Channels," IEEE Journal of Solid-State Circuits, vol. 26, No. 12, Dec. 1991, pp. 1981-1987.
Robert Cypher and C. Bernard Shung, "Generalized Trace-Back Techniques for Survivor Memory Management in the Viterbi Algorithm," Journal of VLSI Signal Processing, 5, 85-94, 1993, pp. 85-94.
Chin Stephen
Rupert Paul N
The Regents of the University of California
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