Low-power, standby mode computer

Details Low-power, standby mode computer Low-power, standby mode computer

1991-06-05

1992-11-10

Fleming, Michael R.

Boots, shoes, and leggings

364707, 364DIG1, 3642731, 36424691, G06F 132

Patent

active

051631539

ABSTRACT:
A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A refresh of the memory is forced before the system refresh operations are discontinued.

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"82C100, 82C101," CHIPS Advance Information, Pub. No. 2-100-B pp. 1-72.

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