Low-power, standby mode computer

Details Low-power, standby mode computer Low-power, standby mode computer

1989-09-28

1991-08-20

Fleming, Michael R.

Boots, shoes, and leggings

3642731, 3642735, G06F 100

Patent

active

050419641

ABSTRACT:
A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A referesh of the memory is forced before the system refresh operations are discontinued.

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"Product Comparison," Infoworld, pp. 52-54, 83, 88, Jun. 3, 1989.
"82C100, 82C101," Chips Advance Information, Publication No. 2-100-B, pp. 1-72.

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