Low power small area PLA

Details Low power small area PLA Low power small area PLA

1982-10-25

1985-04-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307467, 364716, H03K 19177, H03K 19086

Patent

active

045146500

ABSTRACT:
A logic array includes multiple gated current sources for receiving respective logic input signals, each of the gated current sources is coupled to a respective pair of row conductors and sends current to one row conductor or the other of that pair to indicate the state of the received input signal, column conductors are coupled to selectively receive current from any of the row conductors, a circuit generates respective NAND signals indicating when current is received by the column conductors; additional gated current sources respectively receive the NAND signals and send current to respective additional row conductors when the received signals are in predetermined states, additional column conductors selectively receive current from the additional row conductors, and an output circuit is coupled to the additional column conductors for generating respective output NAND signals indicating when current is received therefrom.

REFERENCES:
patent: 3818252 (1974-06-01), Chiba et al.
patent: 4385370 (1983-05-01), Isogai
Radcliffe, "Fusable Diode Array Circuits", IBM Tech. Disc. Bull., vol. 21, No. 1, Jun. 1978, pp. 105-108.
Askin et al., "PLA With Intermixed AND and OR Arrays", IBM Tech. Disc. Bull., vol. 24, No. 8, Jan. 1982, pp. 4291-4292.

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