Low power serial protocol translator for use in multi-circuit bo

Details Low power serial protocol translator for use in multi-circuit bo Low power serial protocol translator for use in multi-circuit bo

1996-09-10

1999-03-02

Sheikh, Ayaz R.

395285, 395309, G06F 1300

Patent

active

058782346

ABSTRACT:
A low power reduced size serial device protocol translator including a slave controller and detection circuit for detecting start and stop conditions on serial data (SDA) and serial clock (SCL) lines in a serial communication system is described. The start and stop condition detector includes two flip-flops; one for providing a signal that indicates when a start condition has occurred on the SDA and SCL lines and another for indicating when a stop condition has occurred. Each of the flip-flops have their data inputs coupled to a high logic level and their enable input coupled to the serial clock line. The first flip-flop for indicating the start condition has its clock input coupled to the inverse of the serial data signal and the second flip-flop for indicating the stop condition has its clock input directly coupled to the serial data signal. As a result, the first and second flip-flops are only enabled and clocked when either a start or stop condition is occurring, resulting in an extremely low power slave controller detection system. The translator of the present invention translates serial signals between slave and master devices having different protocol types. The translator utilizes sub-protocol signals including length information corresponding to the number of data bits being transmitted to the slave device. The translator uses the length information to gate the serial data from the master device to the slave device. The translator allows for reduction of physical interconnections in a master/slave system in which a master devices resides on a first printed circuit board (PCB) and communicates with slave devices on a second PCB having more than one type of serial communication protocol. In this case, the translator resides on the same PCB as the slave devices thus requiring that only the serial buses corresponding to the master device protocol type be physically coupled across the two PCB's interconnection interface.

REFERENCES:
patent: 5513334 (1996-04-01), Alexander
patent: 5592633 (1997-01-01), Casis et al.
patent: 5696994 (1997-12-01), Pang
Patent Abstracts Of Japan, vol. 013, No. 064 (P-827), 14 Feb. 1989 & JP 63 250759 A (Nippon Motorola KK), 18 Oct. 1988, see abstract; figures 1,2.

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