Low power serial link bus architecture

Details Low power serial link bus architecture Low power serial link bus architecture

2006-06-30

2010-10-19

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Substituting specified bit combinations for other prescribed...

C341S100000, C341S101000

Reexamination Certificate

active

07817068

ABSTRACT:
Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.

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International Technology Roadmap for Semiconductors 1999 Edition, 126 pgs.
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