Low power serial link

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Details

C375S242000, C375S244000

Reexamination Certificate

active

08000412

ABSTRACT:
The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.

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patent: 2009/0097864 (2009-04-01), Kershteyn
patent: 2009/0115472 (2009-05-01), Pfaff et al.

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