Low power sense amplifier for programmable logic device

Details Low power sense amplifier for programmable logic device Low power sense amplifier for programmable logic device

1988-09-02

1989-07-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307603, 307594, 307468, 365196, 365208, G11C 702, H03K 17284, H03K 1722, H03K 1726

Patent

active

048517208

ABSTRACT:
The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock is used to provide an initiation signal which starts the propagation of input data through the array. A means is coupled to the clock for sending a dummy data pulse through the second data path upon receipt of the initiation signal, and a detecting means detects the completion of the passage of the dummy data through the second path and supplies a completion signal in response. A switch coupled to the clock, the sense amplifiers and the detecting means powers up the sense amplifiers upon receipt of the initiation signal from the clock, and powers down the sense amplifiers upon receipt of the completion signal from the detecting means. The control circuit of the invention reduces the power consumption of the sense amplifiers because they are powered only during the duration of data transmission, but are otherwise powered down.

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