Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-06-21
2001-05-29
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S051000
Reexamination Certificate
active
06239624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense amplifier for amplifying a signal having a small magnitude, generated in a bit line of a memory, with a low power, specifically, to a low-power two-stage sense amplifier for a memory, the first stage being a differential amplifier for amplifying a weak signal from a bit line of the memory and transmitting the amplified signal to the second stage which sufficiently amplifies the signal from the first stage and passes it through a cutoff circuit, to cut off the power unnecessarily consumed at the first stage, thereby reducing the consumption power.
2. Discussion of Related Art
Highly integrated large-scaled semiconductor devices require large amount of power consumed in chips. While the operation speed of the chip was formerly regarded important more than its consumption power, both factors now become important as portable devices are increasingly used. In a system including a memory chip, this memory chip increasingly consumes power. Thus, it is preferred that the power consumed in the memory chip is reduced.
A conventional sense amplifier is constructed of two stages, the first of which uses a differential amplifier or latch amplifier, the second of which generally uses a latch amplifier. Thus, the sense amplifier is usually divided into a differential amplifier-latch amplifier type and a latch amplifier-latch amplifier type. In the operation characteristic of each of these sense amplifiers, the differential amplifier-latch amplifier amplifies a data signal having smaller magnitude sent from the bit line using the first-stage differential amplifier, and stores the amplified signal using the second-stage latch amplifier to allow the data signal to be used in the next stage. In this configuration, however, the latch amplifier consumes power even after data storage in terms of the characteristic of differential amplifier, resulting in excessive waste of power.
The latch amplifier-latch amplifier type has been proposed for the purpose of solving the problem of the differential amplifier-latch amplifier type sense amplifier. Though this amplifier consumes power less than the differential amplifier-latch amplifier, it is sensitive to offset voltage which is inevitably generated due to the characteristic of memory in terms of the characteristic of latch amplifier, being unable to be operated before the signal from the bit line exceeds a predetermined level. Thus, its operation speed is slower than that of the differential amplifier-latch amplifier. The operation characteristics of the above two different types of sense amplifiers are described in detail in JSSC, Katsuro Sasaki, p1075-p1081. Therefore, there are limitations in reducing consumption power while increasing operation speed in case of the conventional sense amplifiers.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a low-power sense amplifier for a memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a low-power sense amplifier for a memory, the sense amplifier consisting of two stages, the first stage being a differential amplifier for amplifying a weak signal from a bit line of the memory and transmitting the amplified signal to the second stage which sufficiently amplifies the signal from the first stage and passes it through a cutoff circuit, to cut off the power unnecessarily consumed at the first stage, thereby reducing the consumption power.
To accomplish the object of the present invention, there is provided a low-power sense amplifier for a memory, which includes a differential amplifier for sensing and amplifying a weak voltage signal of a bit line connected to a memory cell, and a latch amplifier for storing data inputted thereto, the latch amplifier being operated by the output signal of the differential amplifier, the sense amplifier including a bias means constructed of transistors which are included in the differential amplifier and turned on or turned off by a control signal, the transistors providing a load resistor component required for driving the differential amplifier when it is turned on, and a cutoff means for turning off the transistors constructing the bias means to stop the operation of the differential amplifier when there is a first logic state signal among the output signals of the latch amplifier.
In a preferred embodiment of the present invention, when the transistors constructing the bias means are PMOSs, the first logic state signal is a low-level voltage signal, and the cutoff means is an inverter.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, by Koichiro Ishibashi et al.
Kim Beomsup
Yang Jeong-Sik
Bachman & LaPointe P.C.
Korea Advanced Institute of Science and Technology
Nguyen Hai L.
Wells Kenneth B.
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