Low power sense amplifier

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307279, 307355, 365205, 365208, H03K 3356, H03K 1716

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active

047016442

ABSTRACT:
A low power sense amplifier having bit line sensors for sensing the respective voltage levels of a plurality of bit lines, and a latch connected by data lines to the bit lines sensor, for latching the sensed voltage levels. Circuitry of the amplifier prevents formation of a conductive path to ground through both the bit line sensors and the latch when the sensed voltage levels are latched. This provides a sense amplifier which is low in power consumption, while maintaining a relatively high speed, which is particularly useful in CMOS memories.

REFERENCES:
patent: 3953839 (1976-04-01), Dennison et al.
patent: 4053873 (1977-10-01), Freeman et al.
patent: 4146802 (1979-03-01), Moench
patent: 4238841 (1980-12-01), Clemen et al.
patent: 4412143 (1983-10-01), Patella et al.
patent: 4461965 (1984-07-01), Chin
patent: 4479202 (1984-10-01), Uchida
patent: 4601017 (1986-07-01), Mochizuki et al.
Chao et al, "CMOS Sense-Restore Circuits for One-Device FET Dynamic RAM", IBM T.D.B., vol. 25, No. 10, Mar. 1983, pp. 5088-5091.
Chang, "Dynamic Differential Sense Amplifier Register", IBM T.D.B., vol. 24, No. 4, Sep. 1981, pp. 2199-2200.

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