Low power scannable counter

Details Low power scannable counter Low power scannable counter

1998-04-17

1999-09-28

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

377116, G06M 300

Patent

active

059600527

ABSTRACT:
A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.

REFERENCES:
patent: 5185769 (1993-02-01), Wang
patent: 5339343 (1994-08-01), Hashimoto et al.
patent: 5651040 (1997-07-01), Yu
patent: 5740219 (1998-04-01), O'Dell

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