Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-06-24
2003-09-16
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C327S554000
Reexamination Certificate
active
06621445
ABSTRACT:
BACKGROUND
1. Technical Field
An embodiment of the present invention generally relates to a reference buffer circuit that incorporates switched capacitors. More particularly, an embodiment of the present invention relates to a low power reference buffer circuit in which a second switched capacitor provides a charging voltage to a first switched capacitor.
2. Discussion of the Related Art
A switched capacitor is typically incorporated into a reference buffer circuit by coupling the switched capacitor between the output terminal of a buffer device and a ground potential, as shown in the prior art buffer circuit of
FIG. 5. A
switch connects the switched capacitor to the buffer device and allows the buffer device to provide a reference voltage to the switched capacitor. The sampling frequency (“f
s
”) of the switched capacitor determines the speed with which the buffer device must charge the switched capacitor. Therefore, the buffer device must charge the switched capacitor every 1/f
s
seconds. Assuming that the charging period is governed by a 50% duty cycle clock, the buffer device must charge the switched capacitor within ½ f
s
seconds. For the ½ f
s
second period during which the switched capacitor is not charging, the switched capacitor generally provides its charge to a load circuit. This event occurs when the switch switches from the buffer device to the load circuit.
A buffer device may be a class A amplifier in a unity gain configuration. For example, the output stage would be required to drive:
I=C
1
(
dV/dt
)=10pF(1
V
/1 ns)≈10 mA=>33 mW
Taking f
s
to be 25 MHz, for example, the actual power required is:
I=C
1
(
dV/dt
)=10pF(2.4
V
/40 ns)≈0.6 mA=>2 mW
Therefore, the efficiency is about 6%. Accordingly, this configuration results in an amplifier having very low efficiency, where efficiency is defined as the average power that is delivered to the load circuit divided by the power that is drawn from the amplifier's power supply. For example, the theoretical maximum efficiency of an amplifier in a class A configuration is 25.0%.
Alternatively, a buffer device may be a class AB amplifier, which has a theoretical maximum efficiency of 78.5%. However, this configuration greatly increases the complexity of the design, as compared to a class A configuration, and may not significantly increase actual efficiency. Furthermore, class AB amplifiers are typically not capable of extremely fast operations.
Regardless of a buffer device's configuration, a reference buffer circuit that includes only one switched capacitor requires that the buffer device independently charge the switched capacitor to a certain voltage level before the switched capacitor may be switched to provide a charge to the load circuit. This technique requires the buffer device to draw a significant amount of power from the buffer device's power supply, thereby reducing the efficiency of the reference buffer circuit.
Thus, there is a need for a reference buffer circuit having a buffer device that draws less power from the buffer device's power supply.
REFERENCES:
patent: RE34797 (1994-11-01), Sato et al.
patent: 5440306 (1995-08-01), Tatsumi
Intel Corporation
Jean-Pierre Peguy
Pillsbury & Winthrop LLP
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