Low power redundancy circuit for a memory device

Details Low power redundancy circuit for a memory device Low power redundancy circuit for a memory device

1991-02-12

1993-08-24

Mottola, Steven

Static information storage and retrieval

Powering

Conservation of power

3652257, G11C 1140

Patent

active

052395111

ABSTRACT:
The invention relates to a low power redundancy circuit used in memory device and comprises operation control fuse circuit 47, an OR gate 48, a switching circuit 56, a fuse circuit 45, and a latch-back circuit 57. The latch-back circuit 57 is composed of p channel MOSFET 53 and inverters.

REFERENCES:
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4829480 (1989-05-01), Seo

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