Low power reduced voltage swing latch

Details Low power reduced voltage swing latch Low power reduced voltage swing latch

2002-10-18

2004-07-27

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000

Reexamination Certificate

active

06768365

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to local clock distribution and low power circuit design.
Trademarks: IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
In modern CMOS microprocessors, an important new design obstacle has begun to emerge. Circuits cannot simply be optimized for delay—power consumption is now an additional critical parameter. In modern CMOS microprocessors, a significant portion of the power is dissipated in the clock distribution network, specifically in the local clock nets which drive the latches. With feature sizes decreasing and scale of integration increasing, this problem will continue to worsen. Thus, it can be concluded that improvements in clock distribution techniques, especially local clock distribution, have the potential to lead to major power savings in CMOS microprocessors.
SUMMARY OF THE INVENTION
This invention exploits the direct proportionality of power consumption to the square of the voltage swing and locally distributing a half swing clock to the latches, thereby yielding a 75% decrease in local clock power. In accordance with the preferred embodiment of the invention an improved circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but in accordance with the invention, the preferred embodiment exploits charge sharing to generate the half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. If capacitances have been properly matched, both nodes will settle at Vdd/2.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.


REFERENCES:
patent: 5187686 (1993-02-01), Tran et al.
patent: 5329176 (1994-07-01), Miller et al.
patent: 5751176 (1998-05-01), Sohn et al.
patent: 6208186 (2001-03-01), Nair

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