Low power read scheme for memory array structures

Details Low power read scheme for memory array structures Low power read scheme for memory array structures

2001-04-18

2002-08-27

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S072000

Reexamination Certificate

active

06442099

ABSTRACT:

BACKGROUND OF INVENTION
BACKGROUND ART
A typical modem computer system includes a microprocessor, memory, and peripheral computer resources, i.e., monitor, keyboard, software programs, etc. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions from a computer program.
FIG. 1
shows a prior art diagram of an example of a computer's microprocessor (
20
) that has a central processing unit (“CPU” and also known as “execution unit”) (
22
), a memory controller (
24
) (also known as a “load/store unit”), and on-board, or level 1 (“L1”), cache memory (
26
). The microprocessor (
20
) is connected to external, or level 2 (“L2”), cache memory (
28
), and the processor is also connected to the main memory (
30
) of the computer system. Cache memory is a region of fast memory that holds copies of data.
One goal of the computer system is to execute instructions provided by the computer's users and software programs. The execution of instructions is carried out by the CPU (
22
). Data needed by the CPU (
22
) to carry out an instruction are fetched by the memory controller (
24
) and loaded into the internal registers (
32
) of the CPU (
22
). Upon command from the CPU (
22
), the CPU (
22
) searches for the requested data in the internal registers (
32
). If the requested data is not available in the internal registers (
32
), the memory controller (
24
) searches for requested data first in the fast on-board cache memory (
26
), then in the slower external cache memory (
28
), and if those searches turn out unsuccessful, then the memory controller (
24
) retrieves the data from the slowest form of memory, the main memory (
30
).
The internal registers (
32
) of the CPU (
22
) are formed by a plurality of register files (“RFs”). Register files are an integral part of a microprocessor (
20
) because they are the local most memory available to the CPU (
22
). Typically, requested data that is in L1 cache (
26
) or L2 cache (
28
) is available to the CPU (
22
) three or more clock cycles after cycle in which the CPU (
22
) made the data request. However, requested data that is in the register files is usually available to the CPU (
22
) during the same cycle in which the CPU (
22
) made the data request. Therefore, the speed and performance of the register files is a significant factor in determining the overall speed and performance of the microprocessor (
20
).
Register files are generally arranged in one or more memory arrays. A memory array is a structure in which a plurality of storage cells are arranged such that data in each storage cell can be accessed by the selection of one or more bit lines that are used to read data from the memory array. Often, an array of register file cells is partitioned into a plurality of subsets of rows, with each subset connected to a respective local bit line segment.
FIG. 2
shows a prior art segmented bit line structure of a register file. In a segmented bit line structure, groups of register file cells are segmented along a bit line. For example, in the segmented bit line structure (
40
) shown in
FIG. 2
, register file cells (
42
,
44
,
46
,
48
,
50
,
52
) are segmented into a plurality of segments (
41
,
45
,
49
). Each segment (
41
,
45
,
49
) is connected to a respective local bit line segment (
43
,
47
,
51
).
The bit line segments (
43
,
47
,
51
) are connected in series, with the first bit line segment (
43
) connected to the input of a first sense amplifier (also referred to as “first local sense amplifier”) (
54
). The output of the first local sense amplifier (
54
) is connected to the second bit line segment (
47
), which is, in turn, connected to the input of a second sense amplifier (also referred to as “second local sense amplifier) (
56
). The output of the second local sense amplifier (
56
) is connected to the last bit line segment (
51
), which is, in turn, connected to the input of a global sense amplifier (
58
). The global sense amplifier (
58
) generates an output, OUT, of the segmented bit line structure (
40
).
The local and global sense amplifiers (
54
,
56
,
58
) each have a precharge input, PRE, that is used to precharge the bit line segment connected to their respective inputs. Thus, each local bit line segment (
43
,
47
,
51
) has its own sense amplifier and precharge. This is necessary, because, due to the relatively small size of register file cells, register file cells cannot discharge bit lines very fast, i.e., register file cells are relatively slow when putting data on a bit line, and therefore, sense amplifiers are used to detect small changes on a bit line and output a full data value based on such bit line value changes caused by register file cells. Moreover, because register files need to be very fast for the reasons discussed above, the use of sense amplifiers increases the speed of accessing data as opposed to waiting for a register file cell to fully discharge a bit line. The function of the sense amplifier, in essence, is to “sense” the data in a particular register file cell. However, those skilled in the art will understand that increasing the speed of accessing data in a memory array, or that of virtually any other computer system component, requires increased power consumption.
Each register file cell (
42
,
44
,
46
,
48
,
50
,
52
) has a respective read access transistor (
60
,
62
,
64
,
66
,
68
,
70
), which is used to access data stored within the respective register file cell. The widths of these read access transistors (
60
,
62
,
64
,
66
,
68
,
70
) are equal to each other.
Each bit line segment (
43
,
47
,
51
) is particularly loaded (
59
) due to read access transistor capacitance and the high interconnect resistance and capacitance due to the length of each bit line segment (
43
,
47
,
51
). Because each bit line segment (
43
,
47
,
51
) is heavily loaded, the time it takes to discharge a particular bit line segment is longer than the time it would take if that bit line segment was less loaded or not loaded at all.
Referring still to
FIG. 2
, when data is accessed from a particular register file cell, the read access transistor in that register file cell is used to discharge the bit line segment to which it is connected depending upon the value stored within the register file cell. While the register file cell discharges a bit line segment, a local sense amplifier, which has its input connected to the bit line segment, outputs a data value based on whether that bit line segment input remains precharged or is getting discharged. Thereafter, the data from the local sense amplifier ripples through the local bit line segments and local sense amplifiers in the remaining plurality of segments to the global sense amplifier, which, in turn, outputs the data value. Typically, the global sense amplifier is designed to handle the accumulation of parasitic capacitance on the local bit line segments.
FIG. 3
shows a prior art differential bit line structure of a register file. In a differential bit line structure, register file cells have differential outputs which are connected to differential bit lines, respectively. For example, in the differential bit line structure (
80
) shown in
FIG. 3
, each register file cell (
82
,
84
,
86
,
88
,
90
,
92
) is connected to two differential bit lines (
81
,
83
) that both serve as inputs to a differential sense amplifier (
94
).
The differential sense amplifier (
94
) has a precharge input, PRE, that is used to precharge particular nodes (not shown) within the differential sense amplifier (
94
). Further, the differential sense amplifier (
94
) generates an output, OUT, of the differential bit line structure (
80
).
Each respective register file cell (
82
,
84
,
86
,
88
,
90
,
92
) has two access transistors that have complementary inputs (
87
and
89
,
91
and
93
,
95
and
97
,
99
and
101
,
103
and
105
,
107
and
109
). The widths of these access transistors (
87
and
89
,
91
and
93
,
95
and
97
,
99
and
10

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