Low power push-pull driver

Details Low power push-pull driver Low power push-pull driver

1991-02-12

1992-06-09

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, H03K 1716, H03K 1760, H03K 19003

Patent

active

051210010

ABSTRACT:
A push-pull driver circuit operative with two input logic signals of opposite sense has a first bipolar transistor with a base terminal connected to a first input signal, and an emitter terminal connected to a second bipolar transistor which takes the place of the emitter resistor in the usual construction of an emitter follower circuit. During an activation of the first transistor to pass current, this being the pull-up stage, the second transistor is in a quiescent state to develop a voltage drop provided by current flow from the first transistor. A current mirror maintains a small quiescent current in the second transistor so that it can be activated rapidly upon occurrence of the pull-down transition. During a deactivation of the first transistor to terminate current flow in the first transistor, the voltage drop across the second transistor decreases, this being the pull-down stage. The voltage drop across the second transistor serves as an output signal of the driver circuit. During the pull down stage, the second transistor is activated momentarily via the capacitance of a back-biased transistor to pass current for rapid reduction of the voltage drop across the second transistor, this being in response to the second input signal. To avoid placing the second transistor in a state of saturation, a bypass transistor is connected across the base-collector terminal of the second transistor in the reverse direction of current flow in the second transistor to prevent the development of excessive base drive to the second transistor.

REFERENCES:
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patent: 4766399 (1988-08-01), Davis et al.
patent: 4835420 (1989-05-01), Rosky
C. K. Chuang et al., "High-Speed ECL Circuit", IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, pp. 374-380.
Ostaszewski et al., "Sea-Of-Cells ECL Arrays Come of Age", VLSI Systems Design, Nov. 1988, pp. 18, 22, 24, 28, and 32.

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