Low power pulse-triggered flip-flop

Details Low power pulse-triggered flip-flop Low power pulse-triggered flip-flop

2011-06-14

2011-06-14

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S212000

Reexamination Certificate

active

07961024

ABSTRACT:
A low power pulse-triggered flip-flop comprises a latch containing a first conductive line and a first connection point and a pulse generator linking to the latch. The pulse generator includes a first N-transistor, a second N-transistor, a third N-transistor, a first inverter and a first P-transistor located on the first conductive line. The first N-transistor is connected to the first connection point and first conductive line. The second N-transistor and the third N-transistor are connected to the first conductive line, a second conductive line and a third conductive line. The first inverter is connected to the second conductive line. The present invention aims to reduce leakage power in a high level fabrication process, and can save power consumption and power-delay-product more than 17% over the conventional pulse triggered flip-flop, and also provides a smaller size of total transistors to lower average leakage current power consumption by 2.4 times.

REFERENCES:
patent: 6278308 (2001-08-01), Partovi et al.
patent: 7345519 (2008-03-01), Hirata

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