Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-07-24
2003-04-22
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S306000
Reexamination Certificate
active
06553397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to systems and methods of digital filtering, and in particular to low-power pulse-shaping digital filters.
2. Description of the Related Art
A pulse-shaping digital filter is a digital system consisting of a data rate expander (that inserts zeros between successive input bits) followed by a digital filter operating at the higher data rate. The system accepts an input stream of symbols which, in the most elementary form, is a stream of one-bit data, and produces an output stream of B-bit data (where B is a fixed positive integer) having a waveform suitable for processing by a digital-to-analog converter (DAC). The DAC yields an analog signal whose waveform contains the original bit-stream's information while having its frequency content appropriately bandlimited for transmission through some given communication channel.
Pulse-shaping filters, both analog and digital, have been well studied in the literature for several decades and their importance in the implementation of practical communication systems has only increased as the interest in transmitting digital data has increased. The recent popular interest in wireless digital communication systems such as digital cellular telephones has highlighted the need for digital filter implementations that minimize power dissipation. The present invention satisfies that need.
SUMMARY OF THE INVNTION
To address the requirements described above, the present invention discloses a method, apparatus, article of manufacture, and a memory structure for implementing a low-power digital filter.
The method comprises the steps of successively delaying and mapping each of the input values {x
0
, x
1
, . . . , X
N−1
} to create tap values {t
0
, t
1
, . . . , t
N−1
}, multiplying each of the tap values {t
0
, t
1
, . . . , t
N−1
} by A•{h
0
, h
1
, . . . , h
N−1
} to produce {At
0
h
0
,At
1
h
1
, . . . ,At
N−1
h
N−1
} wherein values {h
0
,h
1
, . . . , h
N−1
} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency and the efficiency of hardware implementation by, for example, reducing the number of operations performed in filtering the input data stream, summing the values {At
0
h
0
,At
1
h
1
, . . . ,At
N−1
h
N−1
} to produce
∑
k
=
0
N
-
1
At
k
h
k
,
biasing the summed values {At
0
h
0
,At
1
h
1
, . . . ,At
N−1
,h
N−1
} to compensate for the multiplied tap values {At
0
h
0
, At
1
h
1
, . . . ,At
N−1
h
N−1
} to produce a digital filter output.
The article of manufacture comprises means for performing the above method steps.
The apparatus comprises an interconnected series of k stages wherein k={1,2, . . . , N−1}. Each of the stages comprises a delay element z
k
31 1
having a delay element input and a delay element output, a weighting element having a weighting element input and a weighting element output, wherein a gain of the weighting element is selected to be a product of a gain h
k
required to achieve a desired digital filter response, and a factor A selected to improve computational and hardware efficiency, and a summation element having a first summation element input, a second summation element input, and a summation element output. The apparatus further comprises a leading gain element with a gain h
0
required to achieve a desired digital filter frequency response, and a factor A selected to improve computational and hardware efficiency. The leading gain element has a leading gain element input coupled to a first stage delay element input and a leading gain element output coupled to a first stage first summation element input. The delay element output of each stage is coupled to the gain element input of the stage and the gain element output of each stage is coupled to the second summation element input of the stage. The delay element output of each stage except the last (N−1 stage) is coupled to the delay element input of the following stage and the summation element output of each stage except the last is coupled to the first summation element input of the following stage. The summation element output of the last stage provides the digital filter output. The digital filter's input is connected to the delay element input of the first stage. A bias summation element modifies the above-described structure by coupling another summation element between the leading gain element output and the first stage summation element input. A bias to compensate for the modified weighting element outputs is provided at the bias summation element.
REFERENCES:
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patent: 4751666 (1988-06-01), Gillingham
patent: 5953241 (1999-09-01), Hansen et al.
Chevillat, Pierre R. et al., “Optimum FIR Transmitter and Receiver Filters for Data Transmission over Band-Limited Channels,” IEEE Transactions on Communications, vol. Com-30, No. 8, Aug. 1982, pp. 1909-1915.
Kuo, Tzu-Chieh et al., “A Programmable Interpolation Filter for Digital Communications Applications,” Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, May 31-Jun. 3, 1998, Monterey, CA, IEEE, 1998, vol. II, pp. II-98-II-100.
Kuo, Tzu-Chieh, “A Programmable Interpolation Filter for Digital Communication Applications,” Thesis, Master of Science in Electrical Engineering, University of California, Los Angeles, CA, 1996, pp. xi, 1-51.
Moreau de Saint-Martin, Francois et al., “Design of Optimal Linear-Phase Transmitter and Receiver Filters for Digital Systems,” IEEE, 1995, pp. 885-888.
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Thompson, Charles D. et al., “A Digitally-Corrected 20b Delta-Sigma Modulator,” IEEE International Solid-State Circuits Conference, Session 11/Oversampled Data Conversion/Paper TP 11.5, IEEE 1994, pp. 194-195.
Vaidyanathan, P.P., “Mulirate Systems and Filter Banks,” Prentice Hall, Englewood Cliffs, NJ 07631, pp. 118-134, undated.
Kuskie C. et al. (1995) “A Decimation Filter Architecture for GHz Delta-Sigma Modulators,” IEEE Int'l Symposium on Circuits and Systems, pp. 953-956.
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Wasserman Larry S.
Willson, Jr. Alan N.
Gates & Cooper LLP
Mai Tan V.
Pentomics, Inc.
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