Low power priority encoder

Details Low power priority encoder Low power priority encoder

2001-04-09

2001-10-23

Tran, Andrew Q. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C365S189070, C365S189080, C365S230080, C365S230020

Reexamination Certificate

active

06307767

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a priority encoder for a content addressable memory (CAM) array.
2. Discussion of Related Art
CAM cells are defined as memory cells that are addressed in response to their content, rather than by a physical address within an array.
FIG. 1
is a block diagram of a conventional memory array formed using twelve CAM cells. The CAM cells are labeled M
X,Y
, where X is the row of the array, and Y is the column of the array. Thus, the array includes CAM cells M
0,0
to M
2,3
. Each of the CAM cells is programmed to store a data bit value. In the described example, the data bit value stored in each CAM cell is indicated by either a “0” or a “1” in brackets. For example, CAM cells M
0,0
, M
0,1
, M
0,2
and M
0,3
store data bit values of 0, 1, 0 and 0, respectively. Each row of CAM cells is coupled to a common match line. For example, CAM cells M
0,0
, M
0,1
, M
0,2
and M
0,3
are coupled to match line MATCH
0
.
The array of CAM cells is addressed by providing a data bit value to each column of CAM cells. Thus data bit values D
0
, D
1
, D
2
and D
3
are provided to columns
0
,
1
,
2
and
3
, respectively. Note that complementary data bit values D
0
#, D
1
#, D
2
# and D
3
# are also provided to columns
0
,
1
,
2
and
3
, respectively. If the data bit values stored in a row of the CAM cells match the applied data bit values D
0
-D
3
, then a match condition occurs. For example, if the data bit values D
0
, D
1
, D
2
and D
3
are 0, 1, 0 and 0, respectively, then the data bit values stored in the CAM cells of row
0
match the applied data bit values. Under these conditions, the MATCH
0
signal is asserted true (e.g., high). Because the applied data bit values D
0
, D
1
, D
2
and D
3
do not match the data bit values store in the CAM cells of rows
1
or
2
, the MATCH
1
and MATCH
2
signals are de-asserted false (e.g., low). The match signals MATCH
0
-MATCH
2
can be used for various purposes, such as implementing virtual addressing, in a manner known to those skilled in the art.
FIG. 2
is a block diagram of a conventional CAM System
1
that includes a 64 Kbit CAM array
10
and an associated priority encoder
11
. CAM array
10
includes 1024 rows and 64 columns of CAM cells. A 64-bit data input signal D[
63
:
0
] is provided from an input/output (I/O) circuit (not shown) to CAM array
10
. Each row of CAM cells in CAM array
10
simultaneously compares its contents with the input data signal D[
63
:
0
] in the manner described above in connection with FIG.
1
. If a match is detected in any of the rows, CAM array
10
asserts a corresponding match control signal. More specifically, if a match is detected in row N of CAM array
10
, then match control signal MATCH_N is asserted, where N is an integer between 0 and 1023.
More than one of the match control signals can be asserted during a comparison operation. For example, match control signals MATCH_
1
, MATCH_
125
and MATCH_
1000
may be asserted during the same comparison operation. All of the match control signals are provided to priority encoder
11
. Priority encoder
11
determines which one of the asserted match control signals has priority. In response, priority encoder
11
provides a 10-bit output address A[
9
:
0
] that corresponds with the asserted match control signal determined to have priority. The output address A[
9
:
0
] is provided to the I/O circuitry (not shown).
FIG. 3
is a block diagram of a 1 Mbit CAM system
100
that includes sixteen CAM arrays
101
-
116
identical to CAM array
10
(FIG.
2
). Each of the sixteen CAM arrays
101
-
116
receives the input data signal D[
63
:
0
] and simultaneously generates the appropriate match control signals. Priority encoder
120
receives the match control signals from all of the CAM arrays
101
-
116
. In response, priority encoder
120
generates a
14
-bit output address A[
13
:
0
].
CAM system
100
consumes a significant amount of power. In general, CAM arrays
101
-
116
consume about 2.5 Watts. Priority encoder
120
also typically consumes about 2.5 Watts. The I/O circuitry associated with CAM system
100
consumes about 1 Watt. This is a significant amount of power to be consumed by a memory system. Consequently, CAM arrays are typically limited to smaller capacities than 1 Mbit (e.g., 1 Kbit).
It would therefore be desirable to have a CAM system having a relatively large capacity, but which consumes less power than a conventional CAM system having the same capacity.
SUMMARY
Accordingly, the present invention provides a CAM system that includes a plurality of CAM arrays that are assigned different priority levels. Each CAM array generates a plurality of match control signals, wherein each of the CAM arrays asserts a match control signal for each detected match. The CAM system also includes a plurality of latch circuits, each being coupled to receive the match control signals from a corresponding CAM array. In one embodiment, there are four latch circuits coupled to receive the match control signals provided by four corresponding CAM arrays.
A latch control circuit is also coupled to receive the match control signals from the CAM arrays. In response, the latch control circuit causes one and only one of the latch circuits to latch the match control signals received from the corresponding CAM array. The latch circuit that latches the match control signals is the latch circuit corresponding with the highest priority CAM array to assert a match control signal. In one embodiment, the latch circuit is controlled by a latch enable signal. Power savings are realized because only one latch enable signal is asserted for any compare operation. Further power savings are realized because only one of the latch circuits switches its stored match control signals during a compare operation.
In a particular embodiment, the latch control circuit includes a plurality of match detector circuits and a plurality of hit logic circuits. Each of the match detector circuits is coupled to receive the match control signals from a corresponding CAM array. If any of the match control signals received by a match detector circuit is asserted, then the match detector circuit asserts a corresponding hit signal. Each hit signal has a priority corresponding with the priority of the CAM array providing the match control signals.
Each of the hit logic circuits is coupled to receive a hit signal from a corresponding match detector circuit, as well as all other hit signals having a higher priority. The hit logic circuit that receives the highest priority asserted hit signal from its corresponding match detector circuit asserts a corresponding latch enable signal, which causes one and only one latch circuit to latch the match control signals received from the corresponding CAM array. All other hit logic circuits de-assert their corresponding latch enable signals, thereby disabling their corresponding latch circuits.
The CAM system also includes plurality of priority encoders, each being coupled a corresponding latch circuit. The priority encoders generate a corresponding intermediate priority address in response to match control signals stored in the corresponding latch circuit. Because only one of the latch circuits stores a new set of match control signals during any compare operation, only one priority encoder will provide a different intermediate priority address during any given compare operation. This results in further power savings within the CAM system.
In another embodiment, each of the hit logic circuits include a latch for storing the hit signal received from the corresponding match detector circuit as a latched hit signal. The latched hit signals are subsequently used to route an output address of the compare operation from the CAM system. By latching the hit signals, it is not necessary for the hit signals to be asserted for the entire duration of the compare operation.
An output logic circuit is coupled to rec

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