Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-01-12
2002-10-08
Malzahn, David H. (Department: 2187)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06463453
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to integrated circuits, and more specifically to a modified Booth's recoder for use in a microcontroller Multiply-Accumulate Unit.
BACKGROUND OF THE INVENTION
Multiply/accumulate units (MACs) are used to perform multiplication of two input operands and the result is added to the accumulator. They are heavily used in many DSP applications and more specifically are used to compute Fast Fourier Transforms.
One current method of implementing multiplication in a MAC unit is the use of a modified Booth's algorithm. It would be helpful to deactivate the multiplier array in a MAC either fully or partially when it is not in use. This is because the multiplier array consumes a significant amount of power and this power could be significantly reduced if the multiplier array were to be either fully or partially deactivated when not in use. One prior art method of reducing power consumption is to gate the clock signal so that data communication between registers is ignored during unanticipated calculation cycles. This technique theoretically operates to reduce the power consumption of a MAC. This approach is reasonably well accepted, but it can be quite complex to design a MAC circuit with proper clock skewing when using this gated clocking scheme.
Another prior art method for designing a low power MAC is to use a comparator to identify when one of the input operands is a binary 0, 1, or −1 value and bypass the known result to the MAC output. This method allows the multiplier array to turn off when any of these special operands (0, +1, −1) is encountered. However, this approach requires an additional logic for the comparator and the power is only reduced when one of the operands must be negative 1, positive 1, or 0.
An improved methodology for implementing a MAC unit using a modified Booth's recoder with some additional gates that can easily and efficiently deactivate the MAC multiplier array when not needed would be advantageous. Such a methodology could significantly reduce the power consumption of an integrated circuit implementing a multiply-accumulate unit (MAC).
REFERENCES:
patent: 5241492 (1993-08-01), Girardeau, Jr.
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patent: 5574672 (1996-11-01), Briggs
patent: 5661673 (1997-08-01), Davis
patent: 5734601 (1998-03-01), Chu
patent: 5787029 (1998-07-01), Angel
patent: 5818743 (1998-10-01), Lee et al.
Malzahn David H.
Motorola Inc.
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