Low-power phase-locked-loop and method using quadrature...

Details Low-power phase-locked-loop and method using quadrature... Low-power phase-locked-loop and method using quadrature...

2005-04-26

2005-04-26

Pascal, Robert (Department: 2817)

Oscillators

Polyphase output

C331S034000, C331S076000

Reexamination Certificate

active

06885253

ABSTRACT:
A phase-locked loop includes a voltage-controlled oscillator (VCO) to generate a plurality of quadrature-phase signals at one-half an output frequency in response to bias signals. The VCO also includes a times-two multiplier biased by the bias signals to generate the output frequency from the quadrature-phase signals. The bias signals include a load-element bias signal to concurrently bias load elements of buffer stages of the VCO and substantially identical load elements of the multiplier. The bias signal also include a current-source bias signal to concurrently bias current sources of the buffer stages of the VCO and a substantially identical buffer stage of the multiplier. The VCO operating at one-half the output frequency together with the multiplier may consume less power than the VCO when operating at the output frequency.

REFERENCES:
patent: 5576715 (1996-11-01), Litton et al.
patent: 6208875 (2001-03-01), Damgaard et al.
patent: 6329882 (2001-12-01), Fayneh et al.
patent: 6344778 (2002-02-01), Nakamura et al.
patent: 20040005869 (2004-01-01), See et al.

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