Low power phase lock loop clocking circuit for battery powered s

Details Low power phase lock loop clocking circuit for battery powered s Low power phase lock loop clocking circuit for battery powered s

1995-01-05

1996-08-20

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 1A, 331 2, 331 17, 331 25, 327105, 327147, 327156, 360 51, 375376, 455260, H03L 707, H03L 708, H03L 710, H03L 716

Patent

active

055482503

ABSTRACT:
According to the present invention, a PLL circuit is designed to include an active mode, a sleep mode and an idle mode. In the idle mode, the PLL draws substantially less power than that in the active mode. In order to return to the designed operating frequency immediately, the PLL periodically refreshes itself in this mode of operation. The power consumption of the PLL is dependent upon the ratio of on-time to off-time which is a fraction of the power consumed in the active mode. Preferably, the PLL is designed to receive an external clock signal as a reference clock from which it develops the internal system clock. The PLL also receives a lower frequency refresh signal for activating a refresh operation during the idle mode. The PLL can power itself down after completing a single phase compare operation. The refresh signal which can be derived from a real time clock must be synchronized to the external reference clock. Thus, the PLL includes a zero-phase-restart circuit.

REFERENCES:
patent: 4816776 (1989-03-01), Kessler
patent: 4914695 (1990-04-01), Martin
patent: 5339278 (1994-08-01), Irwin et al.
patent: 5373254 (1994-12-01), Nakauchi et al.
patent: 5396521 (1995-03-01), Minami

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