Low power peak detector/buffer with fast charge-up time

Details Low power peak detector/buffer with fast charge-up time Low power peak detector/buffer with fast charge-up time

1989-11-27

1991-02-26

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307359, 307546, H03K 5153

Patent

active

049964488

ABSTRACT:
A peak detector circuit that provides a signal at an output terminal which represents the most positive peak voltage level applied at an input terminal. Comparator circuit is coupled to the input terminal and to the output terminal to determine which voltage signal thereof is more positive to provide an output current whenever the supplied input voltage exceeds the voltage at the output terminal. The output current is then amplified for providing a current to a capacitor circuit for developing a voltage across the capacitor equal to the positive peak voltage level applied at the input terminal. A buffer circuit coupled to the capacitor circuit transforms the voltage across capacitor circuit to the output terminal and includes a clamping circuit for clamping coupled between the output terminal and the comparator circuit to prevent the comparator circuit output from saturating whenever the voltage applied at the input terminal is less than that appearing at the output terminal.

REFERENCES:
patent: 3643110 (1972-02-01), Thompson
patent: 4533844 (1985-08-01), Miller et al.
patent: 4603299 (1986-07-01), Monett
patent: 4720643 (1988-01-01), Embree et al.
N. D. Nguyen, "Simple Peak Detector", IBM Technical Disclosure Bulletin, vol. 27, No. 2, Jul. 1984, pp. 1368-1369.

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