Low power partitioned PLA

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307467, 307443, 364716, H03K 19177, H03K 19013, H03K 19086

Patent

active

045061734

ABSTRACT:
A logic array includes a plurality of gated current sources which receive respective input signals, each of said gated current sources is coupled to a respective row conductor and sends current to that row conductor when the received input signal is in a predetermined state; the respective row conductors are partitioned into several groups; a respective high capacitance column conductor is provided for each group; within each group, diodes selectively couple current from the row conductors to the respective high capacitance column conductor; a low capacitance column conductor is provided; and a circuit generates current on the low capacitance column conductor representing the logical NAND of selected input signals when current is coupled from any group of row conductors to the high capacitance column conductor for that group.

REFERENCES:
patent: 3818252 (1974-06-01), Chiba et al.
patent: 4385370 (1983-05-01), Isogai
patent: 4433331 (1984-02-01), Kollaritsch
Askin et al., "PLA with Segmented Lines for Faster Signal Propagation", IBM Tech. Disc. Bull., vol. 24, No. 7B, Dec., 1981, p. 3898.
Greenspan, "Multiple Partitioned Programmable Logic Array", IBM Tech. Disc. Bull., vol. 19, No. 5, Oct., 1976, pp. 1780-1781.
Whitley, "PLA Having OR-Array Bit Partitioning", IBM Tech. Disc. Bull., vol. 24, No. 6, Nov. 1981, pp. 2747-2748.

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