Low power parallel multiplier for complex numbers

Details Low power parallel multiplier for complex numbers Low power parallel multiplier for complex numbers

1996-03-29

1997-12-02

Elmore, Reba I.

Boots, shoes, and leggings

G06F 752

Patent

active

056943490

ABSTRACT:
A high speed, low power parallel multiplier is described. The parallel multiplier includes specialized hardware circuitry designed to perform complex multiplication operations at high speeds. The parallel multiplier requires significantly less die area than conventionally required, which results in reduced manufacturing costs and reduced power consumption.

REFERENCES:
patent: 4858164 (1989-08-01), Schildhorn
patent: 5262976 (1993-11-01), Young et al.
patent: 5500811 (1996-03-01), Corry
Weste, Neil H.E., and Eshraghian, Kamran, "Principles of CMOS VLSI Design" pp. 17-19, 542-560, 2nd Edition, Addison-Wesley Publishing, 1993.

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