Low-power parallel multiplier

Details Low-power parallel multiplier Low-power parallel multiplier

1989-01-20

1991-01-01

Malzahn, David H.

Boots, shoes, and leggings

364707, G06F 752

Patent

active

049823558

ABSTRACT:
A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.

REFERENCES:
patent: 3900724 (1975-08-01), McIver et al.
patent: 4369500 (1983-01-01), Fette
patent: 4441158 (1984-04-01), Kanuma
patent: 4598382 (1986-07-01), Sato
patent: 4736335 (1988-04-01), Barkan
patent: 4748583 (1988-05-01), Noll
"Overview on the Circuit Configuration of Multipliers Performing Parallel Multiplication on which LSIS are Increasingly Used", Nikkei Electronics, May 29, 1978, pp. 76-90.
Hill et al, Digital Systems: Hardware Organization and Design, Second Edition, John Wiley & Sons, pp. 603-606.
Deverell, "Pipeline Iterative Arithmetic Arrays", IEEE Trans. on Computers, Mar. 1975, pp. 317-322.

Affiliated with

Also associated with

Rating

Low-power parallel multiplier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-power parallel multiplier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-power parallel multiplier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2001697