Low power overdriven pass gate latch

Details Low power overdriven pass gate latch Low power overdriven pass gate latch

2005-04-19

2005-04-19

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C361S091100

Reexamination Certificate

active

06882205

ABSTRACT:
A clocking circuit decreases the load on the local clock signals to save power. The load is decreased by altering the structure of the latches. Typically, a passgate style latch is used where both an NFET and a PFET are used to control dataflow. Here, the PFET has been removed and the load is decreased. However, it is difficult to pass a logical1through an NFET and this increases both the rising slew and rising edge delay through the latch. The effect is mitigated, though, by overdriving the local clock block (LCB) local clocks to drive a local clock to the latches by passgates using only NFET transistors in the master latches and slave latches. Overdrivig the NFET gate allows the NFET to pass a full-level logical1signal.

REFERENCES:
patent: 6222387 (2001-04-01), Meng et al.
patent: 6342996 (2002-01-01), Drapkin et al.
patent: 6362942 (2002-03-01), Drapkin et al.
patent: 6392573 (2002-05-01), Volk
patent: 6556487 (2003-04-01), Ratnakumar et al.
patent: 6583646 (2003-06-01), Patel et al.

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