Low power output gate

Details Low power output gate Low power output gate

1990-07-31

1991-06-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307570, H03K 1902

Patent

active

050234790

ABSTRACT:
A low power BiMOS output gate includes an input circuit for passing current through its first and second outputs in response to logic states occurring on first and second input signals which are respectively applied at first and second inputs of the input circuit. A field-effect transistor has first and second electrodes and a control electrode, the control electrode is coupled to the first output of the input circuit, the first electrode is coupled to the second output of the input circuit, and the second electrode is coupled to a first supply voltage terminal. A first resistor is coupled across the second and control electrodes of the field-effect transistor while a second resistor is coupled across the first and second electrodes of the field-effect transistor such that when the first input signal is in a first logic state, the voltage drop occurring across the first resistor will render the field-effect transistor operative wherein the effective resistance of the second resistor is decreased. Also, an output circuit is coupled to the second output of the input circuit for providing an output logic signal at an output terminal of the BiMOS output gate.

REFERENCES:
patent: 4490630 (1984-12-01), Freeman
patent: 4806799 (1989-02-01), Pelley et al.
patent: 4835455 (1989-05-01), Coddington et al.
patent: 4902915 (1990-02-01), Tran
patent: 4945265 (1990-07-01), Estrada

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