Low power output disable circuit for random access memory

Details Low power output disable circuit for random access memory Low power output disable circuit for random access memory

1975-09-02

1977-04-19

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307209, 307279, 307DIG4, 307DIG5, 340173R, H03K 1908, H03K 1934, H03K 3353, G11C 700

Patent

active

040190684

ABSTRACT:
An output circuit including a latch circuit and a push-pull output driver driven by the latch circuit is controlled by disable circuit which disables the output circuit when a random access memory semiconductor chip on which the output circuit is located undergoes an unselected memory cycle, i.e., is unselected. The disable circuit includes a bootstrap NOR gate having a series power switching IGFET coupling its load device to a voltage supply conductor. The power switching IGFET is controlled by the output of the disable circuit so that the disable circuit shuts off its own power at the same time it disables the output latch when the random access memory chip undergoes an unselected memory cycle. Essentially, the disable circuit operates in such a manner that it shuts off its own power and also disables the output circuit in response to a second input signal, conditioned on the occurrence of an earlier first signal.

REFERENCES:
patent: 3697775 (1972-10-01), Kane
patent: 3778784 (1973-12-01), Karp et al.
patent: 3859637 (1975-01-01), Platt et al.
patent: 3906464 (1975-09-01), Lattin

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