Low-power operation of static memory in a read-only mode

Details Low-power operation of static memory in a read-only mode Low-power operation of static memory in a read-only mode

2009-04-14

2010-10-19

Mai, Son L (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S154000, C365S156000, C365S226000

Reexamination Certificate

active

07817490

ABSTRACT:
A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be embedded within a large-scale integrated circuit, for example in combination with a microprocessor and associated circuitry. Upon system control circuitry determining that an SRAM array can be operated in a read-only mode, for example that a large number of read operations are likely to be performed prior to writing to the SRAM array, the power supply voltages applied to the SRAM array are reduced. The array power supply voltage and periphery power supply voltage can be at separate voltages and separately reduced from the read/write mode to the read-only mode. The read-only mode can be readily used for instruction cache memories, and for local instruction memories associated with an embedded microcontroller.

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