Low power on-chip global interconnects

Details Low power on-chip global interconnects Low power on-chip global interconnects

2007-10-26

2009-06-09

Zweizig, Jeffrey S (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

C327S291000

Reexamination Certificate

active

07545205

ABSTRACT:
An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.

REFERENCES:
patent: 6426656 (2002-07-01), Dally et al.
patent: 6614268 (2003-09-01), Dally et al.
patent: 6735130 (2004-05-01), Fan et al.
patent: 6801081 (2004-10-01), Gloaguen et al.
patent: 6836290 (2004-12-01), Chung et al.
patent: 7245173 (2007-07-01), Krasnansky

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