Low-power non-resetable test mode circuit

Details Low-power non-resetable test mode circuit Low-power non-resetable test mode circuit

1997-02-13

1998-09-08

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 81, 327143, 3241581, G01R 3128

Patent

active

058049967

ABSTRACT:
A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch. An integrated circuit pin is coupled to both the test mode circuit and to other circuitry on the integrated circuit not forming part of the test mode circuit.

REFERENCES:
patent: 5111136 (1992-05-01), Kawashima
patent: 5402063 (1995-03-01), Kim
patent: 5675272 (1997-10-01), Chu
patent: 5712575 (1998-01-01), Ma et al.

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