Low power non-overlap two phase complementary clock unit using s

Details Low power non-overlap two phase complementary clock unit using s Low power non-overlap two phase complementary clock unit using s

1996-05-06

1997-06-10

Sheikh, Ayaz R.

G06F 132

Patent

active

056385420

ABSTRACT:
A clock generator which utilizes a SDL, power management circuitry, phase drivers and non-overlap logic all integrated on a single chip to output a set of non-overlapped, complementary clock phases for each processor and for on board peripherals. The present invention also has application for use with multiple discrete processors used on an application or system validation board where one or more of the processors may run at different clock speeds from the others or be stopped. The integrated non-overlap logic reduces the clock skewing among various component on the application board, thus, increasing the overall performance of the system. The present invention is specifically directed to clock generation circuitry including a circuit which receives clock phases generated by a SDL, or from a set of frequency dividers and produces non-overlapped clock phases for each on-board processor and for the on-board peripherals.

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