Low power multiplier for CPU and DSP

Details Low power multiplier for CPU and DSP Low power multiplier for CPU and DSP

1998-02-19

2000-05-16

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 752

Patent

active

06065032&

ABSTRACT:
The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.

REFERENCES:
patent: 4644488 (1987-02-01), Nathan
patent: 4813008 (1989-03-01), Shigehara et al.
patent: 4817029 (1989-03-01), Finegold
patent: 5040139 (1991-08-01), Tran
patent: 5325321 (1994-06-01), Ishida
patent: 5734601 (1998-03-01), Chu
Patent Abstracts of Japan, vol. 097, No. 008, Aug. 29, 1997.

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