Low power MOS RAM address decode circuit

Details Low power MOS RAM address decode circuit Low power MOS RAM address decode circuit

1975-09-02

1977-09-13

Curtis, Marshall M.

Communications: electrical

Digital comparator systems

307215, 340173R, H03K 1934, G11C 1134

Patent

active

040486290

ABSTRACT:
An MOS random access memory chip utilizes a column decode circuit scheme in which a signal derived from a chip select input of the random access memory chip is coupled to the gate of a switching device of dynamic IGFET NOR gates utilized to accomplish the column decoding function. This prevents the bit sense column selection conductor from being affected when an internal column selection clock signal is generated. This results in a substantial savings in power dissipation which would be required if it were necessary to provide circuitry to disable the internal column selection clock generator circuit during an unselected memory cycle.

REFERENCES:
patent: 3747076 (1973-07-01), Martino, Jr.

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